The invention concerns an integrated circuit layout complete with a bus logic unit connected to a data bus, with the bus having at least one activation line for an activation signal, making it possible to activate the bus logic unit via the data bus.
Such a circuit layout is known from German published Patent Application P 44 01 410.4. The integrated circuit layout (IC) described therein features a bus logic unit which can be activated for data transmission via an activation signal which is applied to an activation line of a data bus, that is, the IC can be addressed either as a data source or a data destination by the activation signal. The bus logic unit is used to evaluate data transmitted to the IC, store such data, and control analog or digital IC functions in accordance with such stored data.
The principal disadvantage of this circuit layout is its high power consumption which has a detrimental effect on the ready status of the circuit layout, in particular if this circuit layout is supplied by a battery source.